On the relationship between topography and transistor matching in an analog CMOS technology

A source of drain current mismatch of transistors in a 1.75-μm analog CMOS process is described. Matching of closely spaced transistors is degraded by capacitor topography created prior to the gate level. The effects extend over distances greater than 30 μm and are not reduced by common-centroid layout techniques. Symmetry and wafer position dependencies of the mismatch lead to an explanation of the effect. The topography is thought to interfere with the radial flow of gate level photoresist as it is spun on the wafer. Thickness variations in the photoresist result in channel length variations in the transistors following patterning. Transistor matching is improved by more than a factor of two with the use of a tri-level photoresist sequence at the gate level. Simple theoretical expressions and more exact numerical simulations support the explanation of channel length differences as the source of the measured mismatch. These calculations suggest how mismatch due to channel length, dopant concentration, or gate-oxide thickness may be differentiated with simple current-voltage measurements