Nanotechnology goals and challenges for electronic applications

Author

Bohr, Mark T.

Author_Institution

Intel Corp., Hillsboro, OR, USA

Volume

1

Issue

1

fYear

2002

fDate

3/1/2002 12:00:00 AM

Firstpage

56

Lastpage

62

Abstract

Si metal-oxide-semiconductor field-effect transistor (MOSFET) scaling trends are presented along with a description of today´s 0.13-μm generation transistors. Some of the foreseen limits to future scaling include increased subthreshold leakage, increased gate oxide leakage, increased transistor parameter variability and interconnect density and performance. Basic device and circuit requirements for electronic logic and memory products are described. These requirements need to be kept in mind when evaluating nanotechnology options such as carbon nanotube field-effect transistors (FETs), nanowire FETs, single electron transistors and molecular devices as possible future replacements for Si MOSFETs

Keywords

CMOS logic circuits; CMOS memory circuits; DRAM chips; MOSFET; SRAM chips; carbon nanotubes; elemental semiconductors; integrated logic circuits; integrated memory circuits; leakage currents; molecular electronics; nanotechnology; silicon; single electron transistors; 22 to 130 nm; C; CMOS ICs; DRAM; SET; SRAM; Si; Si MOSFET scaling trends; carbon nanotube FETs; dynamic random access memory; electronic logic products; electronic memory products; field-effect transistors; gate oxide leakage; interconnect density; molecular devices; nanotechnology options; nanowire FETs; single electron transistors; static random access memory; subthreshold leakage; transistor parameter variability; CNTFETs; FETs; Integrated circuit interconnections; Logic circuits; Logic devices; MOSFET circuits; Nanoscale devices; Nanotechnology; Single electron transistors; Subthreshold current;

fLanguage

English

Journal_Title

Nanotechnology, IEEE Transactions on

Publisher

ieee

ISSN

1536-125X

Type

jour

DOI

10.1109/TNANO.2002.1005426

Filename

1005426