A new methodology for design of BiCMOS gates and comparison with CMOS

Author

Raje, Prasad A. ; Saraswat, Krishna C. ; Cham, Kit M.

Author_Institution

Hewlett-Packard Co., Palo Alto, CA, USA

Volume

39

Issue

2

fYear

1992

fDate

2/1/1992 12:00:00 AM

Firstpage

339

Lastpage

347

Abstract

A gate comparison methodology is presented to accurately compare the performance of an arbitrary BiCMOS logic gate with a pure CMOS gate. The concept of the sizing plane (SP) is introduced as a geometrical framework in which the gate comparison methodology is represented. The sizing plane is also shown to be an elegant platform to represent the constraints and tradeoffs in BiCMOS gate design and this is demonstrated by an example for a 1-μm BiCMOS technology. To illustrate the comparison methodology, BiCMOS and CMOS gates are fabricated in a 2-μm BiCMOS technology. The measured performance results are presented and interpreted using the sizing plane. A technology comparison methodology is proposed that predicts the relative performance of a BiCMOS versus a pure CMOS implementation of any arbitrary block of digital logic

Keywords

BIMOS integrated circuits; CMOS integrated circuits; integrated logic circuits; logic design; logic gates; 1 micron; 2 micron; BiCMOS logic gate; CMOS logic gates; constraints; gate comparison methodology; logic design; performance comparison; sizing plane; technology comparison methodology; tradeoffs; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Delay; Design methodology; Helium; Inverters; Logic design; Logic gates; Visualization;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.121692

Filename

121692