ESD failure modes: characteristics mechanisms, and process influences

Electrostatic discharge (ESD) failure modes in advanced CMOS processes have been electrically and physically characterized, and an analysis has been made of the mechanisms of each of the main failure modes. The physical failure modes have been related to the electrical degradation and, therefore, the electrical signatures of the damage mechanisms have been obtained. The distribution of the electrical characteristics after ESD stress, for a given process or design variation, can then be used to identify freak failures and process defects. Investigations of the influence of processing steps such as silicides, lightly doped drains (LDDs), thin gate oxides, bird´s-beak suppression, and barrier metallization on the electrical damage characteristics and the failure modes are presented and analyzed