Title :
A high-performance 0.5-μm BiCMOS technology for fast 4-Mb SRAMs
Author :
Hayden, James D. ; Mele, Thomas C. ; Perera, Asanga H. ; Burnett, David ; Walczyk, Fred W. ; Lage, Craig S. ; Baker, Frank K. ; Woo, Michael ; Paulson, Wayne ; Lien, Mitch ; See, Yee-Chaung ; Denning, Dean ; Cosentino, Stephen J.
Author_Institution :
Motorola Inc., Austin, TX, USA
fDate :
7/1/1992 12:00:00 AM
Abstract :
A high-performance 0.5-μm BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 μm2 by creating self-aligned bit-sense and Vss contacts. A WSix polycide emitter n-p-n transistor with an emitter area of 0.8×2.4 μm2 provides a peak cutoff frequency (fT) of 14 GHz with a collector-emitter breakdown voltage (BVCFO) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase fT and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process
Keywords :
BIMOS integrated circuits; SRAM chips; integrated circuit technology; 0.5 micron; BiCMOS technology; ECL gate delays; WSix polycide emitter; base channeling tail; collector-emitter breakdown voltage; collector-substrate capacitance; emitter area; four-transistor SRAM bit cell size; knee current; npn transistor; peak cutoff frequency; polysilicon; selectively ion-implanted collector; self-aligned bit-sense; BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Capacitance; Cutoff frequency; Delay; MOS devices; MOSFETs; Random access memory;
Journal_Title :
Electron Devices, IEEE Transactions on
