A high-performance 0.5-μm BiCMOS technology for fast 4-Mb SRAMs

Author

Hayden, James D. ; Mele, Thomas C. ; Perera, Asanga H. ; Burnett, David ; Walczyk, Fred W. ; Lage, Craig S. ; Baker, Frank K. ; Woo, Michael ; Paulson, Wayne ; Lien, Mitch ; See, Yee-Chaung ; Denning, Dean ; Cosentino, Stephen J.

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

39

Issue

7

fYear

1992

fDate

7/1/1992 12:00:00 AM

Firstpage

1669

Lastpage

1679

Abstract

A high-performance 0.5-μm BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 μm² by creating self-aligned bit-sense and V_ss contacts. A WSi_x polycide emitter n-p-n transistor with an emitter area of 0.8×2.4 μm² provides a peak cutoff frequency (f_T) of 14 GHz with a collector-emitter breakdown voltage (BV_CFO) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f_T and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process

Keywords

BIMOS integrated circuits; SRAM chips; integrated circuit technology; 0.5 micron; BiCMOS technology; ECL gate delays; WSi_x polycide emitter; base channeling tail; collector-emitter breakdown voltage; collector-substrate capacitance; emitter area; four-transistor SRAM bit cell size; knee current; npn transistor; peak cutoff frequency; polysilicon; selectively ion-implanted collector; self-aligned bit-sense; BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Capacitance; Cutoff frequency; Delay; MOS devices; MOSFETs; Random access memory;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.141233

Filename

141233