Yield enhancement effects of boosted dual word-line (BDWL) scheme for high density DRAMs

This paper describes the yield enhancement effects of a boosted dual word-line (BDWL) scheme for the first Al wiring in high density DRAMs, with a defect density model and a yield model used for comparison with that of the commonly used word-shunt (WS) scheme. Additionally, the yield of first Al wiring with a step height between memory cell array and peripheral circuit regions is also estimated. The yield estimation demonstrated that the yield enhancement effect of the wide first Al wiring for the BDWL scheme was comparable with or surpassed that of the redundancy for the WS scheme yield, when the first Al wiring pitch over the memory cell array or a BDWL scheme was over 4 times wider than that of the WS scheme. The yield estimation with step height indicated that the first Al wiring yield of the BDWL scheme with the step height exceeded that of the WS scheme with the step height of zero, even if using some global planarization technology