• DocumentCode
    756090
  • Title

    Reducing the cost variance in life testing of integrated circuits

  • Author

    Leung, Yiu-Wing

  • Author_Institution
    Dept. of Comput., Hong Kong Polytech. Univ., Hung Hom, Hong Kong
  • Volume
    9
  • Issue
    1
  • fYear
    1996
  • fDate
    2/1/1996 12:00:00 AM
  • Firstpage
    149
  • Lastpage
    152
  • Abstract
    The cost of life testing of integrated circuits (ICs) varies statistically. It is desirable to reduce the testing cost variance in order to reduce the chance of paying a testing cost that is much larger than the mean. In this paper, we study two methods for reducing the testing cost variance. The first method uses the technique of weighted sum of objective functions to integrate the objective of minimizing the mean testing cost and the objective of minimizing the testing cost variance. In the second method, the test engineer inspects the progress of life testing iteratively, collects failure information and then estimates the expected remaining testing cost. If this cost is unacceptably large, he replaces the failed ICs by the functioning ones and/or adds extra IC testers
  • Keywords
    concurrent engineering; failure analysis; integrated circuit testing; iterative methods; life testing; production testing; IC testing; cost variance; expected remaining testing cost; failure information; iterative methods; life testing; objective functions; weighted sum; Circuit testing; Costs; Fabrication; Integrated circuit testing; Job shop scheduling; Life testing; Processor scheduling; Pulp manufacturing; Semiconductor device manufacture; Virtual manufacturing;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/66.484297
  • Filename
    484297