A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques

Author

Honda, Kazutaka ; Furuta, Masanori ; Kawahito, Shoji

Author_Institution

Res. Inst. of Electron., Shizuoka Univ., Hamamatsu

Volume

42

Issue

4

fYear

2007

fDate

4/1/2007 12:00:00 AM

Firstpage

757

Lastpage

765

Abstract

This paper presents a low-power low-voltage 10-bit 100-MSample/s pipeline analog-to-digital converter (ADC) using capacitance coupling techniques. A capacitance coupling sample-and-hold stage achieves high SFDR with 1.0-V supply voltage at a high sampling rate. A capacitance coupling folded-cascode amplifier effectively saves the power consumption of the gain stages of the ADC in a 90-nm digital CMOS technology. The SNDR and the SFDR are 55.3 dB and 71.5 dB, respectively, and the power consumption is 33 mW

Keywords

CMOS digital integrated circuits; amplifiers; analogue-digital conversion; low-power electronics; sample and hold circuits; 1 V; 10 bit; 33 mW; 90 nm; SFDR; SNDR; capacitance coupling techniques; class-AB amplifier; digital CMOS technology; folded-cascode amplifier; low-power A/D converter; pipeline ADC; pipeline analog-to-digital converter; sample-and-hold stage; signal-to-noise-and-distortion ratio; spurious-free dynamic range; Analog-digital conversion; CMOS technology; Capacitance; Pipelines; Power dissipation; Prototypes; Sampling methods; Signal to noise ratio; Switches; Voltage; Capacitance coupling; class-AB amplifier; low distortion; low power; low voltage; pipeline analog-to-digital converter;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.891683

Filename

4140586