Title :
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory
Author :
Morishita, Fukashi ; Hayashi, Isamu ; Gyohten, Takayuki ; Noda, Hideyuki ; Ipposhi, Takashi ; Shimano, Hiroki ; Dosaka, Katsumi ; Arimoto, Kazutami
Author_Institution :
Renesas Technol. Corp., Hyogo
fDate :
4/1/2007 12:00:00 AM
Abstract :
A twin-transistor random access memory (TTRAM) can provide high speed, low power and high density with CMOS compatible SOI process. However it is difficult to handle as the unified memory required for advanced SoC because it needs the simple control sensing operation for memory compiler, higher cell efficiency, and lower voltage operation for dynamic frequency and voltage control. Enhanced TTRAM (ET2RAM) applies the actively body-bias control technique to realize the low voltage array operation, and never require the negative voltage source. The ET2RAM can realize both 263 MHz at 0.8 V and 10.2 mW at 0.5 V random-cycle operation, higher cell efficiency, and process scalability. It also provides the simple control method suitable for the unified macro for system-level power management SoC with keeping the merits of TTRAM as CMOS compatibility
Keywords :
CMOS memory circuits; low-power electronics; random-access storage; storage management chips; system-on-chip; 0.5 V; 0.8 V; 10.2 mW; 263 MHz; CMOS compatibility; CMOS compatible SOI process; ET2RAM; body-bias control technique; capacitorless DRAM; configurable enhanced TTRAM macro; low voltage array operation; system-level power management; system-on-chip; twin-transistor random access memory; unified macro; unified memory; CMOS process; Dynamic voltage scaling; Energy management; Frequency; Low voltage; Memory management; Power system management; Random access memory; Read-write memory; Voltage control; Capacitorless DRAM; SOI; power management; system-on-chip; unified memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.891677
