Title :
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits
Author :
Ohbayashi, Shigeki ; Yabuuchi, Makoto ; Nii, Koji ; Tsukamoto, Yasumasa ; Imaoka, Susumu ; Oda, Yuji ; Yoshihara, Tsutomu ; Igarashi, Motoshige ; Takeuchi, Masahiko ; Kawashima, Hiroshi ; Yamaguchi, Yasuo ; Tsukamoto, Kazuhiro ; Inuishi, Masahide ; Makino
Author_Institution :
Renesas Technol. Corp., Hyogo
fDate :
4/1/2007 12:00:00 AM
Abstract :
In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mum2 SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology
Keywords :
CMOS memory circuits; SRAM chips; design for manufacture; low-power electronics; nanoelectronics; system-on-chip; 65 nm; 6T-SRAM cell stability; 8 Mbit; SoC embedded 6T-SRAM; assist circuits; circuit techniques; design for manufacturability; high-yield 8M-SRAM; low stand-by power CMOS technology; read operation stabilizing circuit; sub-100-nm CMOS technology; write operation stabilizing circuit; CMOS technology; Circuit stability; Degradation; Manufacturing; Moore´s Law; Paper technology; Production systems; Random access memory; Shape control; Transistors; 65-nm CMOS; 6T-SRAM; Assist circuit; CMOS; SRAM; Vth curve; Vth-variability; embedded SRAM;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.891648
