Title :
Direct tunneling RAM (DT-RAM) for high-density memory applications
Author :
Kuo, Charles ; King, Tsu-Jae ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA
fDate :
7/1/2003 12:00:00 AM
Abstract :
A new approach to reducing the tunnel oxide thickness in floating gate memories is introduced for RAM applications. Experimental measurements and two-dimensional (2-D) device simulations are used to investigate the operating principles of a direct tunneling RAM (DT-RAM) cell. DT-RAM targets memory applications in which manufacturability, scalability, low-power, high-density, and long retention times are important considerations.
Keywords :
MOS memory circuits; circuit simulation; low-power electronics; random-access storage; tunnelling; 2D device simulations; DT-RAM; direct tunneling RAM; floating gate memories; high-density memories; high-density memory applications; low-power memories; manufacturability; retention times; scalability; tunnel oxide thickness; Capacitance measurement; Charge carrier processes; Electron traps; Interface states; Nonvolatile memory; Photonic band gap; Random access memory; Read-write memory; Tunneling; Voltage;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2003.814017
