Title :
Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories
Author :
Denq, Li-Ming ; Hsing, Yu-Tsao ; Wu, Cheng-Wen
Author_Institution :
Nat. Tsing Hua Univ.
Abstract :
Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell´s defect information. A failure bitmap viewer provides visual information for design and process diagnostics.
Keywords :
circuit testing; embedded systems; network routing; system-on-chip; diagnostic syndrome; high routing penalty; memory cell defect information; memory core diagnosis; multiple heterogeneous embedded memories; Bandwidth; Built-in self-test; Centralized control; Circuit testing; Information analysis; Logic testing; Random access memory; Read-write memory; Routing; Wireless communication; MECA system; at-speed testing; diagnostic syndrome; failure bitmap; hybrid BIST; routing penalty; routing-area overhead; yield enhancement;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2009.37
