Fast track to power talks - The need to prevent power-saving techniques from tripping up chip designers has led to an unprecedented level of cooperation among the design-tool vendors and their users. But there is still potential for conflict

The need to prevent power-saving techniques from tripping up chip designers has led to an unprecedented level of cooperation among the design-tool vendors and their users. But there is still potential for conflict. If there is a word associated with `standards´, it´s not normally `fast´. All too often, sorely needed technology standards proceed at a pace that can see them outmaneuvered by tectonic plates. Infighting leads to delays until some companies break ranks and try to create a de facto standard or the filibusters finally work out that they are losing sales from the delay. When it comes to a standard that will let chip designers express how their creations will handle power-saving modes, we may be in for something of a record. Not just one but two specifications will be ready in a matter of weeks and there may even be enough willingness among tools vendors to work together that those two specifications will merge into single recognised standard