Understanding VLSI bit serial multipliers

Author

Balsara, Poras T. ; Harper, David T., III

Author_Institution

Dept. of Electr. Eng., Texas Univ., Dallas, TX, USA

Volume

39

Issue

1

fYear

1996

fDate

2/1/1996 12:00:00 AM

Firstpage

19

Lastpage

28

Abstract

The efficient design of bit serial multipliers is necessary in many applications areas as diverse as digital communications and the implementation of artificial neural networks. Because of these applications, bit serial architectures are a part of courses in computer arithmetic, very large scale integration (VLSI) architectures, and digital signal processing. Comprehensive descriptions for three bit serial algorithms for signed multiplication are presented. The primary difference among the three algorithms is in the recoding of the multipliers, Each bit serial multiplier is systematically derived from its equivalent parallel multiplier found in textbooks. Furthermore, complete CMOS layouts for the three multipliers are constructed, simulated, and compared

Keywords

CMOS integrated circuits; VLSI; computer science education; data flow computing; digital arithmetic; educational courses; electronic engineering education; multiplying circuits; parallel architectures; VLSI architectures; VLSI bit serial multipliers; artificial neural networks; bit serial architectures; complete CMOS layouts; computer arithmetic courses; digital communications; digital signal processing; education; equivalent parallel multiplier; signed multiplication; textbooks; three bit serial algorithms; Algorithm design and analysis; Application software; Artificial neural networks; Computer architecture; Costs; Digital arithmetic; Digital signal processing; MOS devices; Signal processing algorithms; Very large scale integration;

fLanguage

English

Journal_Title

Education, IEEE Transactions on

Publisher

ieee

ISSN

0018-9359

Type

jour

DOI

10.1109/13.485228

Filename

485228