Title :
A 1.1-mW-RX
-dBm Sensitivity CMOS Transceiver for Bluetooth Low Energy
Author :
Masuch, J. ; Delgado-Restituto, Manuel
Author_Institution :
Inst. of Microelectron. of Seville (IMSE), CNM, Seville, Spain
Abstract :
This paper presents a fully integrated low-power 130-nm CMOS transceiver tailored to the Bluetooth low energy (BLE) standard. The receiver employs a passive front-end zero-IF architecture, which is directly driven by a quadrature voltage-controlled oscillator (QVCO) without any buffering stage. The QVCO, embedded in a fractional-N phase-locked loop (PLL), employs a passive RC network to cancel the parasitic magnetic coupling between the two cores so as to keep the quadrature phase error below 1.5°. The PLL exhibits a high loop bandwidth of 1 MHz to sufficiently reduce the frequency pulling effects due to close-by interferers. The transmitter uses a direct-modulation Gaussian frequency-shift keying scheme in which small PMOS-based cells modulate the output signal of one of the cores of the QVCO. In the baseband section, the transceiver employs a 4-bit phase-domain ADC based on novel linear-combiner topology to generate the required phase rotations. The proposed combiner operates in current domain and does not employ resistors, leading to a power- and area-efficient demodulator implementation. The complete receiver achieves a sensitivity of - 81.4 dBm and fulfills the BLE requirements on interference blocking. It consumes 1.1 mW from a 1.0-V supply and has a similar power efficiency as recent super-regenerative receivers that are much more susceptible to interferers. The transmitter delivers 1.6-dBm output power to a differential 100 Ω and consumes 5.9 mW, which implies a total efficiency of 24.5%.
Keywords :
Bluetooth; CMOS integrated circuits; Gaussian processes; analogue-digital conversion; demodulators; frequency shift keying; modulation; phase locked loops; radio receivers; radio transceivers; resistors; voltage-controlled oscillators; BLE requirements; BLE standard; PMOS-based cells; QVCO; area-efficient demodulator implementation; bluetooth low energy; direct-modulation Gaussian frequency-shift keying scheme; fractional-N PLL; fractional-N phase-locked loop; frequency pulling effects; front-end zero-IF architecture; fully integrated low-power CMOS transceiver; high loop bandwidth; interference blocking; linear-combiner topology-based 4-bit phase-domain ADC; parasitic magnetic coupling; passive RC network; phase rotations; power 1.1 mW; power 5.9 mW; power efficiency; quadrature phase error; quadrature voltage-controlled oscillator; resistance 100 ohm; sensitivity CMOS transceiver; size 130 nm; super-regenerative receivers; voltage 1 V; Capacitance; Couplings; Frequency modulation; Phase locked loops; Receivers; Transceivers; Bluetooth low energy (BLE); Gaussian frequency-shift keying (GFSK); direct modulation; low-power transceiver; magnetic coupling cancellation; passive receiver; phase ADC; quadrature voltage-controlled oscillator (QVCO); zero IF;
Journal_Title :
Microwave Theory and Techniques, IEEE Transactions on
DOI :
10.1109/TMTT.2013.2247621