Transient and Thermal Analysis on Disturbance Immunity for 4 Surrounding Gate 1T-DRAM With Wide Trenched Body

This paper presents a one-transistor dynamic random access memory (1T-DRAM) based on a novel surrounding-gate transistor with wide trenched body (WT-SGT). This 1T-DRAM exhibits favorable transient performance after word line (WL)/bit line (BL) disturbance, which is verified using Sentaurus TCAD 12.0. The proposed memory cell can be fabricated with a feature area of 4F² and with processes that are fully compatible with conventional CMOS technology. Extended simulations reveal three key findings. First, the WT-SGT achieves a high-speed programming operation (1.17 ns) at a low operating voltage (1.6 V) and with a programming window that can be further extended by widening its trenched body. Second, the recombination rate is also reduced, thereby yielding an acceptable retention time (RT) of 625.6 ms. Third, the decreased RT after a 100-ns WL/BL disturbance is improved by 33%, as compared with a conventional SGT 1T-DRAM. We, therefore, believe that this new device will become a competitive candidate for use in future DRAM cells.