Title :
A CMOS serial link for fully duplexed data communication
Author :
Lee, Kyeongho ; Kim, Sungjoon ; Ahn, Gijung ; Deog-Kyoon
Author_Institution :
Inter-Univ. Semicond. Res. Center, Seoul Nat. Univ., South Korea
fDate :
4/1/1995 12:00:00 AM
Abstract :
This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 μm CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns
Keywords :
CMOS digital integrated circuits; clocks; data communication; data communication equipment; digital phase locked loops; 1.2 micron; 320 Mbit/s; 500 Mbit/s; CMOS serial link; bidirectional bridge; central charge pump PLL; digital PLL; fully duplexed data communication; low-ratio oversampling; majority voting; multiphase clocks; oversampling; parallel data recovery scheme; process-independent data recovery; pseudo random data patterns; scaled CMOS technology; unidirectional mode operation; Bridges; CMOS technology; Charge pumps; Clocks; Communication cables; Data communication; Phase locked loops; Robustness; Testing; Voting;
Journal_Title :
Solid-State Circuits, IEEE Journal of