A 256-element associative parallel processor

Author

Herrmann, Frederick P. ; Sodini, Charles G.

Author_Institution

Dept. of Electr. Eng., MIT, Cambridge, MA, USA

Volume

30

Issue

4

fYear

1995

fDate

4/1/1995 12:00:00 AM

Firstpage

365

Lastpage

370

Abstract

A 256-element associative processing chip is designed for pixel-parallel image processing and machine vision applications. A five-transistor three-state dynamic memory cell is used, and each processing element has 64 trits of memory. Other processing element components include a function generator, an activity register, and connections to a reconfigurable mesh network and a response resolution subsystem. These are implemented with compact circuits designed within memory pitch constraints. The chip was fabricated in a double-poly CCD-CMOS process and characterized as fully functional. A sample image processing application is demonstrated on a four-chip prototype system

Keywords

CMOS digital integrated circuits; associative processing; charge-coupled device circuits; computer vision; parallel processing; activity register; associative parallel processor; double-poly CCD-CMOS process; function generator; machine vision applications; memory pitch constraints; pixel-parallel image processing; processing element; reconfigurable mesh network; response resolution subsystem; three-state dynamic memory cell; Associative processing; Circuits; Image processing; Machine vision; Memory management; Mesh networks; Pixel; Process design; Registers; Signal generators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.375954

Filename

375954