DocumentCode
759651
Title
A wide-bandwidth low-voltage PLL for PowerPC microprocessors
Author
Alvarez, Jose ; Sanchez, Hector ; Gerosa, Gianfranco ; Countryman, Roger
Author_Institution
Somerset Design Center, Motorola Inc., Austin, TX, USA
Volume
30
Issue
4
fYear
1995
fDate
4/1/1995 12:00:00 AM
Firstpage
383
Lastpage
391
Abstract
A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 μm CMOS technology is described. The PLL supports internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 μs, PLL power dissipation below 10 mW as well as phase error and jitter below ±100 ps have been measured. The total area of the PLL is 0.52 mm 2
Keywords
CMOS digital integrated circuits; clocks; digital phase locked loops; frequency synthesizers; jitter; microprocessor chips; 0.5 micron; 3.3 V; 6 to 175 MHz; CMOS technology; CPU clock lock range; PowerPC microprocessors; clock frequency ratios; clock synthesizer; jitter; lock times; low-voltage PLL; phase error; power dissipation; static power down modes; CMOS technology; Clocks; Frequency; Jitter; Microprocessors; Phase locked loops; Phase measurement; Power dissipation; Power measurement; Synthesizers;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.375957
Filename
375957
Link To Document