Title :
Optimum architecture for input queuing ATM switches
Author :
Majumder, Satya P. ; Gangopadhyay, Ranjan
Author_Institution :
Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India
fDate :
3/28/1991 12:00:00 AM
Abstract :
An input queueing ATM switch architecture employing the contention resolution called ´scheduling algorithm´ is described. A high efficiency of over 90% can be achieved without any considerable increase in the amount of hardware or contention control speed.
Keywords :
queueing theory; switches; time division multiplexing; asynchronous transfer mode; contention control speed; contention resolution; design tradeoff; efficiency; hardware complexity; input queuing ATM switches; scheduling algorithm;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19910350
