DocumentCode
759690
Title
A 60 mW per Lane, 4 
23-Gb/s 2 
1 PRBS Generator
Author
Laskin, Ekaterina ; Voinigescu, Sorin P.
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont.
Volume
41
Issue
10
fYear
2006
Firstpage
2198
Lastpage
2208
Abstract
An ultra-low-power, 27-1 PRBS generator with four, appropriately delayed, parallel output streams was designed. It was fabricated in a 150-GHz fT SiGe BiCMOS technology and measured to work up to 23 Gb/s. The four-channel PRBS generator consumes 235 mW from 2.5 V, which results in only 60 mW per output lane. The circuit is based on a 2.5-mW BiCMOS CML latch topology, which, to the best of our knowledge, represents the lowest power for a latch operating above 10 Gb/s. A power consumption and speed comparison of series and parallel PRBS generation techniques is presented. Low-power BiCMOS CML latch topologies are analyzed using the OCTC method
Keywords
BiCMOS logic circuits; Ge-Si alloys; current-mode logic; flip-flops; low-power electronics; random number generation; 150 GHz; 2.5 V; 2.5 mW; 235 mW; 60 mW; BiCMOS technology; CML latch topology; PRBS generator; SiGe; current-mode logic; parallel PRBS generation; parallel output streams; pseudorandom bit sequence generator; BiCMOS integrated circuits; Built-in self-test; CMOS technology; Circuit testing; Circuit topology; Energy consumption; Germanium silicon alloys; Latches; Power generation; Silicon germanium; Current-mode logic; OCTC; SiGe BiCMOS; pseudo-random bit sequence generator; technology scaling;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2006.878112
Filename
1703673
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