Title :
Half-swing clocking scheme for 75% power saving in clocking circuitry
Author :
Kojima, Hirotsugu ; Tanaka, Satoshi ; Sasaki, Katsuro
Author_Institution :
Hitachi America Ltd., San Jose, CA, USA
fDate :
4/1/1995 12:00:00 AM
Abstract :
We propose a half-swing clocking scheme that allows us to reduce power consumption of clocking circuitry by as much as 75%, because all the clock signal swings are reduced to half of the LSI supply voltage. The new clocking scheme causes quite small speed degradation, because the random logic circuits in the critical path are still supplied by the full supply voltage. We also propose a clock driver which supplies half-swing clock and generates half VDD by itself. We confirmed that the half-swing clocking scheme provided 67% power saving in a test chip fabricated with 0.5 μm CMOS technology, ideally 75%, in the clocking circuitry, and that the degradation in speed was only 0.5 ns by circuit simulation. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction with minimal speed degradation
Keywords :
CMOS digital integrated circuits; clocks; driver circuits; large scale integration; timing circuits; 0.5 micron; CMOS technology; LSI supply voltage; clock driver; clocking circuitry; half-swing clocking scheme; power consumption reduction; power saving technique; CMOS technology; Circuit simulation; Circuit testing; Clocks; Degradation; Driver circuits; Energy consumption; Large scale integration; Logic circuits; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of