DocumentCode :
759753
Title :
Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process
Author :
Chen, Tung-Yang ; Ker, Ming-Dou
Author_Institution :
Nanoelectronics & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Volume :
16
Issue :
3
fYear :
2003
Firstpage :
486
Lastpage :
500
Abstract :
The layout dependence on ESD robustness of NMOS and PMOS devices has been experimentally investigated in details. A lot of CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection. The main layout parameters to affect ESD robustness of CMOS devices are the channel width, the channel length, the clearance from contact to poly-gate edge at drain and source regions, the spacing from the drain diffusion to the guard-ring diffusion, and the finger width of each unit finger. Non-uniform turn-on effects have been clearly investigated in the gate-grounded large-dimension NMOS devices by using EMMI (EMission MIcroscope) observation. The optimized layout parameters have been verified to effectively improve ESD robustness of CMOS devices. The relations between ESD robustness and the layout parameters have been explained by both transmission line pulsing (TLP) measured data and the energy band diagrams.
Keywords :
CMOS integrated circuits; MOSFET; VLSI; band structure; electrostatic discharge; integrated circuit layout; integrated circuit manufacture; protection; CMOS manufacturing process; EMMI observation; ESD robustness; NMOS devices; PMOS devices; channel length; channel width; deep-submicron CMOS process; electrostatic discharge protection; emission microscope observation; energy band diagrams; finger width; layout parameters dependence; nonuniform turn-on effects; optimized layout rules; second breakdown; snapback; transmission line pulsing measured data; CMOS process; Electrostatic discharge; Energy measurement; Fingers; MOS devices; Manufacturing processes; Microscopy; Protection; Robustness; Transmission line measurements;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2003.815200
Filename :
1219497
Link To Document :
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