Title :
A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers
Author :
Ishibashi, Koichiro ; Takasugi, Koichi ; Komiyaji, Kunihiro ; Toyoshima, Hiroshi ; Yamanaka, Toshiaki ; Fukami, Akira ; Hashimoto, Naotaka ; Ohki, Nagatoshi ; Shimizu, Akihiro ; Hashimoto, Takashi ; Nagano, Takahiro ; Nishida, Takashi
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fDate :
4/1/1995 12:00:00 AM
Abstract :
A 4-Mb CMOS SRAM with 3.84 μm2 TFT load cells is fabricated using 0.25-μm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM´s using TFT load cells
Keywords :
CMOS memory circuits; SRAM chips; differential amplifiers; feedback amplifiers; 0.25 micron; 2.7 V; 4 Mbit; 6 ns; CMOS SRAM; TFT load cells; address access time; boosted cell array architecture; current sense amplifiers; fast static RAMs; low voltage operation; offset-voltage-insensitive amplifiers; Batteries; CMOS technology; Differential amplifiers; Low voltage; Operational amplifiers; Personal digital assistants; Power dissipation; Random access memory; Reduced instruction set computing; Thin film transistors;
Journal_Title :
Solid-State Circuits, IEEE Journal of
