Title :
A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits
Author :
Tachibana, Suguru ; Higuchi, Hisayuki ; Takasugi, Koichi ; Sasaki, Katsuro ; Yamanaka, Toshiaki ; Nakagome, Yoshinobu
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fDate :
4/1/1995 12:00:00 AM
Abstract :
The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM´s. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-μm CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6 ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6 ns
Keywords :
CMOS memory circuits; SRAM chips; cache storage; pipeline processing; synchronisation; 0.25 micron; 16 kbit; 2.5 V; 2.6 ns; cache SRAM; dual-sensing-latch circuits; source-biased self-resetting circuit; synchronization; wave-pipelined CMOS SRAM; CMOS technology; Circuits; Clocks; Delay; Latches; Microprocessors; Pipeline processing; Random access memory; Synchronization; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
