Title :
A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM
Author :
Nambu, Hiroaki ; Kanetani, Kazuo ; Idei, Youji ; Masuda, Toru ; Higeta, Keiichi ; Ohayashi, Masayuki ; Usami, Masami ; Yamaguchi, Kunihiko ; Kikuchi, Toshiyuki ; Ikeda, Takahide ; Ohhata, Kenichi ; Kusunoki, Takeshi ; Homma, Noriyuki
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fDate :
4/1/1995 12:00:00 AM
Abstract :
An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm 2 memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM´s, which have been used as cache and control storages in mainframe computers
Keywords :
BiCMOS memory circuits; SRAM chips; cache storage; crosstalk; emitter-coupled logic; integrated circuit noise; very high speed integrated circuits; 0.3 micron; 0.65 ns; 0.8 ns; 1 Mbit; 72 kbit; BiCMOS inverter; BiCMOS technology; CMOS memory-cell arrays; ECL decoder/driver circuit; ECL-CMOS RAM macro; MOS equalizer; SRAM chip design; cache storage; control storage; crosstalk noise; high-density SRAM; replica memory cell; twisted bit-line structure; ultrahigh-speed operation; write-pulse generator; BiCMOS integrated circuits; CMOS memory circuits; Cache storage; Decoding; Delay effects; Driver circuits; Equalizers; Inverters; Random access memory; Read-write memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
