Title :
A source sensing technique applied to SRAM cells
Author :
O´Connor, Kevin J.
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
fDate :
4/1/1995 12:00:00 AM
Abstract :
A new CMOS cell design is proposed, analyzed, and implemented in an ASIC macrocell generator to evaluate the performance and reliability of sensing the ground return current produced in the cell during read access. Both single and dual port cell configurations are studied for static noise margin (SNM), writing requirements, and source offset voltage effects. To frame the advantages and differences of the SSS cell, a comparison is made to several conventional SRAM cells. Noise margins are found to be the same or better than conventional cells, and where design allows cell device ratio optimizations, single ended access cells can generate greater SNM than differential cells. The source sensing technique was evaluated by inserting the new cell in a 0.5 μm ASIC memory block and tested on standard ASIC test sets
Keywords :
CMOS memory circuits; SRAM chips; application specific integrated circuits; integrated circuit design; network topology; 0.5 mum; ASIC macrocell generator; CMOS cell design; SRAM cells; dual port cell configurations; ground return current; performance; read access; reliability; single port cell configurations; source offset voltage effects; source sensing; static noise margin; writing requirements; Application specific integrated circuits; Design optimization; Macrocell networks; Noise generators; Performance analysis; Random access memory; Signal to noise ratio; Testing; Voltage; Writing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
