Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique

Author

Ker, Ming-Dou ; Chen, Shih-Lun

Author_Institution

Nanoelectronics & Gigascale Syst. Lab., Nat. Chiao Tung Univ., Hsinchu

Volume

41

Issue

10

fYear

2006

Firstpage

2324

Lastpage

2333

Abstract

An nMOS-blocking technique for mixed-voltage I/O buffer realized with only 1timesV_DD devices can receive 2timesV_DD, 3timesV_DD, and even 4timesV_DD input signal without the gate-oxide reliability issue is proposed. In this paper, the 2timesV_DD input tolerant mixed- voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.25-mum 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3timesV_DD input tolerant mixed-voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.13-mum 1-V CMOS process to serve 1/3-V mixed-voltage interface. The proposed nMOS-blocking technique can be extended to design the 4timesV_DD, 5timesV_DD, and even 6timesV_DD input tolerant mixed-voltage I/O buffers. The limitation of the nMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process

Keywords

CMOS integrated circuits; buffer circuits; integrated circuit design; p-n junctions; semiconductor device breakdown; 0.13 micron; 0.25 micron; 1 V; 2.5 V; 3 V; 5 V; CMOS process; NMOS-blocking technique; breakdown voltage; gate-oxide reliability; hot-carrier degradation; junction breakdown; mixed-voltage I/O buffer; mixed-voltage interface; pn-junction; CMOS process; CMOS technology; Circuits; Costs; Degradation; Hot carriers; Leakage current; MOS devices; Power supplies; Voltage; Gate-oxide reliability; hot-carrier degradation; interface; junction breakdown; mixed-voltage I/O buffer;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.881546

Filename

1703687