BIST test pattern generators for two-pattern testing-theory and design algorithms

Testing for delay and CMOS stuck-open faults requires two-pattern tests, and typically a large number of two pattern tests are needed. Built-in self-test (BIST) schemes are attractive for comprehensive testing of such faults. BIST test pattern generators (TPGs) for two-pattern testing, should be designed to ensure high transition coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal transition coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs that maximize transition coverage under any given TPG size constraint. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two pattern testing, independent of their feedback rules. Based on the necessary sufficient conditions, efficient algorithms to design optimal TPGs for two-pattern testing have been developed. Experiments on benchmark circuits indicate that TPGs designed using the procedures outlined in this paper obtain high robust path delay fault coverage in short test lengths