Title :
Improved First-Order Time-Delay Tanlock Loop Architectures
Author :
Al-Qutayri, Mahmoud A. ; Al-Araji, Saleh R. ; Al-Moosa, I.
Abstract :
This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of acquisition speed, locking range and resilience to frequency disturbances. The first-order TDTL was also implemented on a field programmable gate array (FPGA). The real-time results from the FPGA implementation are in agreement with the ones obtained through simulation
Keywords :
delay lock loops; digital phase locked loops; field programmable gate arrays; FPGA implementation; TDTL design; acquisition speed; delay switching; field programmable gate array; first-order time-delay digital tanlock loop; frequency disturbance resilience; gain adaptation; locking range; loop architectures; Circuits; Delay; Demodulation; Field programmable gate arrays; Frequency; Mobile communication; Performance gain; Phase locked loops; Resilience; Sampling methods; Architecture; loop; performance; tanlock;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2006.880316
