Title :
VLSI architecture for SAR data compression
Author :
Jeong, H. ; Park, J.H. ; Ryu, H.Y. ; Kwon, J.B. ; Oh, Y.
Author_Institution :
Dept. of Electr., POSTECH, Pohang, South Korea
fDate :
4/1/2002 12:00:00 AM
Abstract :
As a step towards a real-time signal aperture radar (SAR) correlator, custom very large scale integration (VLSI) architectures are developed. Considering the extremely short word length of the data, we derive three architectures with massive parallelism in bit space. Unlike frequency methods, no. degradation is introduced during convolution. Optimized for time and space, they are highly suited to VLSI implementation, and a small architecture with 80 taps operating at 10 MHz has been built using an FPGA
Keywords :
VLSI; adders; application specific integrated circuits; computational complexity; convolution; correlators; data compression; field programmable gate arrays; image coding; image processing equipment; parallel architectures; pipeline processing; radar computing; radar imaging; synthetic aperture radar; 2D filter; ASIC chip; FPGA; Kronecker delta function; PCI board; SAR data compression; VLSI architecture; accumulator; adder tree; area-time computational complexity; azimuth compression; carry look-ahead adder; carry propagate adder; carry save adder; computational requirements; convolution; data recovery; fast architectures; frequency domain; highly regular architectures; image compression; massive parallelism; pipelining; range compression; real-time signal aperture radar correlator; sea-of-gates library; software package; time domain; Application specific integrated circuits; Computer architecture; Concurrent computing; Correlators; Data compression; Digital signal processing chips; Filtering; Filters; Synthetic aperture radar; Very large scale integration;
Journal_Title :
Aerospace and Electronic Systems, IEEE Transactions on
DOI :
10.1109/TAES.2002.1008977
