Mesa-sidewall gate leakage in InAlAs/InGaAs heterostructure field-effect transistors

InAlAs/InGaAs HFETs fabricated by conventional mesa isolation have a potential parasitic gate-leakage path where the gate metallization overlaps the exposed channel edge at the mesa sidewall. The existence of this path has been proven by fabricating special heterojunction diodes with different mesa-sidewall gate-metal overlap lengths. It is found that sidewall leakage is a function of the crystallographic orientation of the sidewall, and increases with channel thicknesses, sidewall overlap area, and InAs mole fraction in the channel. In HFETs fabricated alongside the diodes, sidewall leakage increased the subthreshold and forward gate leakage currents, and reduced the breakdown voltage