DocumentCode :
761068
Title :
Three architectural models for compiler-controlled speculative execution
Author :
Chang, Pohua P. ; Warter, Nancy J. ; Mahlke, Scott A. ; Chen, William Y. ; Hwu, Wen-Mei W.
Author_Institution :
Intel Corp., USA
Volume :
44
Issue :
4
fYear :
1995
fDate :
4/1/1995 12:00:00 AM
Firstpage :
481
Lastpage :
494
Abstract :
To effectively exploit instruction level parallelism, the compiler must move instructions across branches. When an instruction is moved above a branch that it is control dependent on, it is considered to be speculatively executed since it is executed before it is known whether or not its result is needed. There are potential hazards when speculatively executing instructions. If these hazards can be eliminated, the compiler can more aggressively schedule the code. The hazards of speculative execution are outlined in this paper. Three architectural models: restricted, general, and boosting, which have increasing amounts of support for removing these hazards are discussed. The performance gained by each level of additional hardware support is analyzed using the IMPACT C compiler which performs superblock scheduling for superscalar and superpipelined processors
Keywords :
exception handling; optimising compilers; parallel programming; parallelising compilers; IMPACT C compiler; architectural models; compiler-controlled speculative execution; conditional branches; exception handling; instruction level parallelism; static code scheduling; superblock scheduling; superpipelined processors; superscalar processors; Boosting; Buffer storage; Dynamic scheduling; Hardware; Hazards; Parallel processing; Performance analysis; Pipeline processing; Processor scheduling; Reliability engineering;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.376164
Filename :
376164
Link To Document :
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