Title :
An 85mW 14-bit 150MS/s pipelined ADC with a merged first and second MDAC
Author :
Li Weitao ; Li Fule ; Yang Changyi ; Li Shengjing ; Wang Zhihua
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
A low-power 14-bit 150MS/s analog-to-digital converter (ADC) is presented for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multiplying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further. The dedicated sample-and-hold amplifier (SHA) is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the performance. The prototype ADC is fabricated in a 130nm CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 mW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
Keywords :
CMOS integrated circuits; analogue-digital conversion; buffer circuits; calibration; digital-analogue conversion; operational amplifiers; sample and hold circuits; CMOS process; SHA; blind calibration; capacitor sharing; communication applications; digital-to-analog converter; first multiplying digital-to-analog converter; high-speed reference buffer; linearity errors; low jitter clock receiver; low-power analog-to-digital converter; pipelined ADC; power 11 mW; power 17 mW; power 57 mW; power 85 mW; range scaling; sample-and-hold amplifier; second MDAC; single-stage opamp; size 130 nm; voltage 1.3 V; word length 14 bit; Calibration; Capacitors; Clocks; Discharges (electric); Linearity; Noise; Receivers; CMOS analog integrated circuits; analog-to-digital conversion; calibration; high speed and high resolution; low power; pipelined analog-to-digital converter;
Journal_Title :
Communications, China
DOI :
10.1109/CC.2015.7112040
