A memory efficient belief propagation decoder for polar codes

Polar codes have become increasingly popular recently because of their capacity achieving property. In this paper, a memory efficient stage-combined belief propagation (BP) decoder design for polar codes is presented. Firstly, we briefly reviewed the conventional BP decoding algorithm. Then a stage-combined BP decoding algorithm which combines two adjacent stages into one stage and the corresponding belief message updating rules are introduced. Based on this stage-combined decoding algorithm, a memory-efficient polar BP decoder is designed. The demonstrated decoder design achieves 50% memory and decoding latency reduction in the cost of some combinational logic complexity overhead. The proposed decoder is synthesized under TSMC 45nm Low Power CMOS technology. It achieves 0.96 Gb/s throughput with 14.2mm² area when code length N=2¹⁶ which reduces 51.5% decoder area compared with the conventional decoder design.