DocumentCode
762020
Title
Optical receiver array in silicon bipolar technology with selfaligned, low parasitic III/V detectors for DC-1 Gbit/s parallel links
Author
Weiland, J. ; Melchior, H. ; Kearley, M.Q. ; Morris, C.R. ; Moseley, A.M. ; Goodwin, M.J. ; Goodfellow, R.C.
Author_Institution
Swiss Federal Inst. of Technol., Zurich, Switzerland
Volume
27
Issue
24
fYear
1991
Firstpage
2211
Lastpage
2213
Abstract
A 1*8 element III-V photodetector/silicon bipolar circuit receiver array has been fabricated using a selfaligning, low parasitic, flipchip solder bond hybridisation process. Receiver elements operate at data rates up to 1 Gbit/s with an input sensitivity of -23 dBm at 1.3 mu m wavelength, and with negligible interchannel crosstalk. An overall delay of 1.5 ns was measured between optical input and digital output.
Keywords
VLSI; bipolar integrated circuits; digital integrated circuits; emitter-coupled logic; flip-chip devices; optical interconnections; receivers; soldering; 0 to 1 Gbit/s; 1.3 micron; 1.5 ns; III/V detectors; Si bipolar technology; data rates; flipchip solder bond hybridisation process; input sensitivity; low parasitic; optical receiver array; overall delay; parallel links; selfaligned; selfaligning; wavelength;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19911368
Filename
109492
Link To Document