Title :
A New Single-Ended SRAM Cell With Write-Assist
Author :
Hobson, Richard F.
Author_Institution :
Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC
Abstract :
A 6T static random access memory (SRAM) cell with a new write-assist (WA) feature is presented. The WA technique reduces the problem of writing a "one" through an nMOS pass device, thereby making a single-ended bit line more attractive. Both active power and leakage power can be significantly reduced. Leakage charge can be pooled to help precharge bit lines. Cell area and performance are competitive with traditional SRAM cell area and performance
Keywords :
CMOS memory circuits; SRAM chips; leakage currents; low-power electronics; 6T static random access memory cell; active power; leakage charge; leakage powered bit lines; nMOS pass device; single-ended SRAM cell; write-assist; CMOS technology; Decoding; Energy consumption; MOS devices; Microprocessors; Random access memory; SRAM chips; System-on-a-chip; Voltage; Writing; Leakage powered bit lines; low leakage static random access memory (SRAM); low power memory; single-ended 6T SRAM cell;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2007.893580
