Title :
Verifying timing consistency in formal specifications
Author :
Bartos, Tibor ; Fristacky, Norbert
Author_Institution :
Dept. of Comput. Sci., Slovak Tech. Univ., Bratislava, Slovakia
Abstract :
The authors´ algorithm formally verifies the rule set that expresses timing discipline in digital system specifications. Their algorithm is based on a higher level behavioral specification model and concerns formal consistency verification at the design level of the system specification development procedure
Keywords :
formal specification; formal verification; hardware description languages; logic CAD; timing; VHDL; algorithm; design; digital system specifications; formal consistency verification; formal specifications; higher level behavioral specification; rule set; timing; timing consistency verification; Circuit synthesis; Formal specifications; Formal verification; Hydrogen; Logic functions; Testing; Time factors; Timing;
Journal_Title :
Design & Test of Computers, IEEE
