Title :
Net scheduling in high-level synthesis
Author :
Prihozhy, Anatoly
Author_Institution :
Dept. of Comput. Syst., State Univ. of Inf. & Radioelectron., Minsk, Byelorussia
Abstract :
A new net scheduling and allocation model generates net schedules that minimize either execution time or resources. The author tested the model within a VHDL-based high-level synthesis system called Ahiles
Keywords :
high level synthesis; logic design; scheduling; Ahiles; allocation model; execution time; high-level synthesis; net scheduling; Circuit synthesis; Control system synthesis; Digital circuits; Hardware; High level synthesis; Multiplexing; Partitioning algorithms; Processor scheduling; Scheduling algorithm; Signal synthesis;
Journal_Title :
Design & Test of Computers, IEEE
