• DocumentCode
    762212
  • Title

    Test synthesis with alternative graphs

  • Author

    Ubar, Raimund

  • Author_Institution
    Dept. of Comput. Eng., Tallinn Tech. Univ., Estonia
  • Volume
    13
  • Issue
    1
  • fYear
    1996
  • Firstpage
    48
  • Lastpage
    57
  • Abstract
    Alternative graphs provide an efficient, uniform model describing the structure, functions, and faults in a wide class of digital circuits and for different representation levels. For test pattern generation, they provide a general theoretical basis for combining high-level approaches, symbolic techniques based on binary decision diagrams, and traditional topological algorithms
  • Keywords
    graphs; logic CAD; logic testing; alternative graphs; binary decision diagrams; high-level approaches; representation levels; symbolic techniques; test pattern generation; topological algorithms; Algorithm design and analysis; Boolean functions; Circuit faults; Circuit synthesis; Circuit testing; Circuit topology; Costs; Design automation; Digital systems; System testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.485782
  • Filename
    485782
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=762212