Segmented Virtual Ground Architecture for Low-Power Embedded SRAM

Author

Sharifkhani, Mohammad ; Sachdev, Manoj

Volume

15

Issue

2

fYear

2007

Firstpage

196

Lastpage

205

Abstract

A new scheme to reduce the power consumption of static random access memories is presented. It is shown that using segmented virtual grounding (SVGND), it is possible to reduce both dynamic and static power consumption. The leakage power of the cells is reduced by reducing the voltage drop over a cell. The dynamic power dissipation is also reduced by eliminating the power consumption due to the discharge of the nondesired neighboring bitlines. The effectiveness of this scheme is compared to recently reported low-power schemes. It is shown that unlike those schemes, SVGND can accommodate multiple words in one row; a significant improvement in soft error rate tolerance

Keywords

SRAM chips; earthing; embedded systems; leakage currents; low-power electronics; power consumption; cells leakage power; dynamic power consumption; dynamic power dissipation; leakage current; low-power embedded SRAM; segmented virtual ground architecture; segmented virtual grounding; soft error rate tolerance; static power consumption; static random access memories; voltage drop; CMOS technology; Computer architecture; Energy consumption; Error analysis; Grounding; Power dissipation; Random access memory; Robustness; SRAM chips; Voltage; Leakage current; low-leakage; low-power; memories; power consumption; random access memories (RAM); static access random memories (SRAM);

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2007.893584

Filename

4142784