• DocumentCode
    762694
  • Title

    A Two-Dimensional Model for Interface Coupling in Triple-Gate Transistors

  • Author

    Akarvardar, Kerem ; Mercha, Abdelkarim ; Cristoloveanu, Sorin ; Gentil, Pierre ; Simoen, Eddy ; Subramanian, Vaidy ; Claeys, Cor

  • Author_Institution
    Inst. of Microelectron., Electromagnetism & Photonics, Minatec-Nat. Polytech. Inst. of Grenoble
  • Volume
    54
  • Issue
    4
  • fYear
    2007
  • fDate
    4/1/2007 12:00:00 AM
  • Firstpage
    767
  • Lastpage
    775
  • Abstract
    The influence of the fin width on substrate-to-gate coupling in long-channel silicon-on-insulator triple-gate transistors is investigated. A complementary analysis, taking into account both the "front coupling" (variation of the front-channel threshold voltage VT1, as a function of the substrate bias VG2) and "back coupling" (variation of the back-channel threshold voltage VT2) as a function of the front-gate bias VG1) characteristics has been carried out. It is shown that the back coupling, as opposed to the front coupling, is highly sensitive to the fin width in narrow-channel devices and can even be used in fin width extraction. Simple analytical 2-D models for the body potential, VT1, and VT2 have been developed to clarify the experimental data, showing in particular the gradual control of the back interface potential by the lateral gates in narrow fins. The model stands as a 2-D generalization of the Lim and Fossum\´s well-known 1-D interface coupling model
  • Keywords
    MOSFET; coupled circuits; silicon-on-insulator; substrates; 2D model; FinFET; back-channel threshold voltage; fin field-effect transistor; fin width extraction; fringing fields; front-channel threshold voltage; interface coupling model; long-channel silicon-on-insulator; multiple-gate transistor; narrow-channel devices; substrate bias; substrate-gate coupling; triple-gate transistors; Analytical models; Data mining; FETs; FinFETs; MOSFETs; Microelectronics; Photonics; Silicon on insulator technology; Threshold voltage; Two dimensional displays; Coupling effects; fin field-effect transistor (FinFET); fin width extraction; fringing fields; multiple-gate transistor; s ilicon-on-insulator (SOI); threshold voltage; triple-gate transistor; two-dimensional (2-D) modeling; undoped body;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2007.892364
  • Filename
    4142867