Title :
Parallel decoding of binary BCH codes
Author_Institution :
Inst. of Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
A parallel decoding procedure for the BCH codes is introduced, which is particularly useful for decoding BCH codes with small error-correcting capability. The high regularity inherent in the scheme enable it to be easily implemented with VLSI circuits.
Keywords :
decoding; information theory; VLSI circuits; binary BCH codes; decoding BCH codes; parallel decoding procedure; small error-correcting capability;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19911375
