Dependence of Device Structures on Latchup Immunity in a High-Voltage 40-V CMOS Process With Drain-Extended MOSFETs

Author

Hsu, Sheng-Fu ; Ker, Ming-Dou

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu

Volume

54

Issue

4

fYear

2007

fDate

4/1/2007 12:00:00 AM

Firstpage

840

Lastpage

851

Abstract

The dependence of device structures on latchup immunity in a 0.25-mum high-voltage (HV) 40-V CMOS process with drain-extended MOS (DEMOS) transistors has been verified with silicon test chips and investigated with device simulation. Layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. It was demonstrated that the drain-extended NMOS with a specific isolated device structure can greatly enhance the latchup immunity. The proposed test structures and simulation methodologies can be applied to extract safe and compact design rule for latchup prevention of DEMOS transistors in HV CMOS process

Keywords

CMOS integrated circuits; MOSFET; elemental semiconductors; silicon; 0.25 micron; 40 V; CMOS process; MOS transistors; Si; device simulation; device structures dependence; drain-extended MOSFET; latchup immunity; silicon test chips; silicon-controlled rectifier; transmission line pulsing; CMOS process; CMOS technology; Circuits; Immune system; MOSFETs; Rectifiers; Silicon; Thyristors; Transistors; Voltage; Drain-extended MOS (DEMOS); high-voltage (HV) CMOS process; l atchup; silicon-controlled rectifier (SCR); transmission line pulsing (TLP);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2007.892013

Filename

4142883