Bit-level systolic imlementation of 1D and 2D discrete wavelet transform [imlementation read as implementation]

The author presents a systolic array architecture for VLSI implementation of the one-dimensional discrete wavelet transform (DWT) which computes both high- and low-pass frequency coefficients in the same clock cycle. The architecture is simple, modular and cascadable for computation of one- or multidimensional DWTs. It needs 62% fewer registers than existing architecture, and the hardware utilisation of the proposed structure is very high. Two systolic architectures are presented for bit-level VLSI implementation of 1D and 2D DWT. Matrix transposition is avoided in the systolic architecture for bit-level VLSI implementation of 2D DWTs.