Title :
A high-fidelity decimator chip for the measurement of sigma-delta modulator performance
Author :
Kale, Izzet ; Morling, Richard C S ; Krukowski, Artun ; Tsang, Chung-Wai
Author_Institution :
Westminster Univ, London, UK
fDate :
10/1/1995 12:00:00 AM
Abstract :
This paper reports on results from the algorithmic design and simulation of a two-path polyphase decimation filter with 24-bit accuracy over the frequency range from dc to 15.2 kHz. The filter is suited for very high precision data conversion and measurement applications. The device reported in this paper has been designed for use with a fourth-order, single-loop, ΣΔ modulator running at 4096 kHz. Results of floating and fixed-point simulations, architectural design, comparative bit-level simulations and silicon implementation of the decimator are also reported, together with a sample baseband measurement of a fourth-order modulator
Keywords :
CMOS digital integrated circuits; IIR filters; all-pass filters; cascade networks; circuit analysis computing; digital arithmetic; floating point arithmetic; sigma-delta modulation; 0 to 15.2 kHz; 24-bit accuracy; 4096 kHz; CMOS filter; IIR all pass filter; algorithmic design; algorithmic simulation; architectural design; bit-level simulation; coefficient design algorithm; decimator cascade; fixed-point simulation; floating-point simulation; fourth-order single-loop ΣΔ modulator; high precision data conversion; high-fidelity decimator chip; magnitude response; measurement applications; sample baseband measurement; sigma-delta modulator performance measurement; silicon implementation; two-path polyphase decimation filter; Algorithm design and analysis; Baseband; Delta-sigma modulation; Digital filters; Digital signal processing; Finite impulse response filter; IIR filters; Passband; Semiconductor device measurement; Silicon;
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
