DocumentCode :
763598
Title :
On the computation of the length-2m discrete cosine and sine transforms via the permuted difference coefficient
Author :
Wei, Ching-Huang ; Chen, Chang-Fuu
Author_Institution :
Dept. of Electr. Eng., Tatung Inst. of Technol., Taipei, Taiwan
Volume :
44
Issue :
2
fYear :
1996
fDate :
2/1/1996 12:00:00 AM
Firstpage :
387
Lastpage :
396
Abstract :
An intrinsic property, wherein the set of numbers formed using the magnitudes of a basis vector´s elements is the same for all basis vectors in a length-2m type-III discrete sine transform (DST) and discrete cosine transform (DCT), is proved. We also show that the set of numbers formed using the magnitudes of any basis vector´s elements in a length-2m type-III DST is the same as that in a length-2m type-III DCT. The same characteristics exist for the length-2m type-IV DST and DCT. A new combinational VLSI architecture that is only composed of adders for implementing the length-2m type-III DST or DCT (DST-III/DCT-III) using the intrinsic property and the permuted difference coefficient (PDC) algorithm is developed. The advantages of this new architecture are high structural regularity, very high speed, and suitability for VLSI realization. The other advanced sequential structure, which is composed of registers, multiplexers, and an accumulator, is also proposed to give a much lower complexity than the combinational structure. This new sequential structure is very suitable for chip-level, microprocessor-based, or VLSI realization. The quantization error that exhibits the effect of the internal finite word-length representations of the input and the coefficient is also analyzed. It is shown that if the length of data sequence is quadrupled, then to maintain the same signal to noise ratio, one additional bit must be added to represent both the input and the coefficient. It is also shown that the roundoff error of the coefficients is less sensitive than that of the inputs
Keywords :
VLSI; adders; combinational circuits; digital signal processing chips; discrete cosine transforms; roundoff errors; shift registers; accumulator; adders; chip-level realisation; coefficient; combinational VLSI architecture; data sequence length; discrete cosine transform; discrete sine transform; internal finite word-length representations; microprocessor-based realisation; multiplexers; permuted difference coefficient algorithm; quantization error; registers; roundoff error coefficients; sequential structure; signal to noise ratio; structural regularity; type-III DCT; type-III DST; very high speed; Discrete cosine transforms; Discrete transforms; Multiplexing; Noise reduction; Quantization; Registers; Roundoff errors; Signal processing algorithms; Signal to noise ratio; Very large scale integration;
fLanguage :
English
Journal_Title :
Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1053-587X
Type :
jour
DOI :
10.1109/78.485934
Filename :
485934
Link To Document :
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