Spatial filtering in flash A/D converters

Author

Pan, Hui ; Abidi, Asad A.

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA

Volume

50

Issue

8

fYear

2003

Firstpage

424

Lastpage

436

Abstract

Averaging networks suppress the random mismatch between the comparators in flash A/D converters (ADCs), but an analytical understanding does not exist, nor a method for optimal design. This paper unifies various forms of offset averaging and derives the optimum by treating the averaging network as a spatial filter. At the optimum, the offsets in terms of LSB are minimized with almost no loss in comparator unity-gain bandwidth. This work leads to an easy-to-follow procedure to design efficient and fast CMOS flash-type ADCs.

Keywords

CMOS integrated circuits; analogue-digital conversion; error correction; high-speed integrated circuits; matched filters; spatial filters; averaging networks; comparator unity-gain bandwidth; fast CMOS ADCs; flash A/D converters; flash-type ADCs; interpolation; offset averaging; random mismatch suppression; resistor network; spatial filtering; Bandwidth; Clocks; Digital signal processing; Filtering; Interpolation; Latches; Signal analysis; Signal to noise ratio; Spatial filters; Spatial resolution;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/TCSII.2003.813584

Filename

1220776