Analysis and minimization of phase noise of the digital hybrid PLL frequency synthesizer

This paper analyzes the phase noise of the digital hybrid phase locked loop (DH-PLL) frequency synthesizer that can give high speed frequency synthesis. Because noise generated by the D/A converter is added to the output phase noise, total phase noise is increased unlike in the conventional PLL. So, the aim of this paper is to minimize output phase noise for pure signal synthesis. Mathematical models of three noise sources such as input reference noise, D/A converter noise due to the quantization error and VCO noise are derived and analysed to get the minimum phase noise. Phase noise analysis of the DH-PLL is studied by the closed loop bandwidth and frequency synthesis division ratio (N). From the analysis and simulation results, we can deduce that the DH-PLL system has optimum performance for phase noise and switching speed. Schematic simulation results by the practical devices are verified to be consistent with the analysis results