• DocumentCode
    765114
  • Title

    All-digital reverse modulation architecture based carrier recovery implementation for GMSK and compatible FQPSK

  • Author

    Gao, Wei ; Feher, Kamilo

  • Author_Institution
    Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
  • Volume
    42
  • Issue
    1
  • fYear
    1996
  • fDate
    3/1/1996 12:00:00 AM
  • Firstpage
    55
  • Lastpage
    62
  • Abstract
    A carrier recovery circuit implementation with an all-digital reverse modulation approach for coherent detection in the GSM/GMSK system as well as the GMSK compatible improved efficiency cross-correlated FQPSK system is presented. The proposed carrier recovery implementation utilizes all-digital reverse modulation circuit in a feedback loop to remove the modulated signal from the received intermediate frequency (IF) signal and to estimate the phase error of this carrier signal using a phase-locked loop (PLL). The digital reverse modulation approach avoids the multipliers required in an analog reverse modulation design, so that it can be implemented in a single chip FPGA. Hardware implementation of the coherent detection demonstrates that cross-correlated FQPSK is completely compatible with GMSK in the system performance and the receiver structure for GSM. Experimental performance evaluations show that the proposed carrier recovery circuit provides a Bit Error Rate (BER) performance within 0.3 dB in a non-linearly amplified channel corrupted by additive white Gaussian noise (AWCN) as compared with the simulated performance of the GSM/GMSK system
  • Keywords
    Gaussian channels; digital phase locked loops; field programmable gate arrays; minimum shift keying; phase estimation; quadrature phase shift keying; signal detection; BER performance; GMSK; additive white Gaussian noise; all-digital reverse modulation architecture; carrier recovery circuit; coherent detection; compatible FQPSK; feedback loop; nonlinearly amplified channel; phase error estimation; phase-locked loop; received intermediate frequency signal; receiver structure; single chip FPGA; system performance; Bit error rate; Digital modulation; Feedback circuits; Feedback loop; Field programmable gate arrays; Frequency estimation; GSM; Phase estimation; Phase locked loops; Phase modulation;
  • fLanguage
    English
  • Journal_Title
    Broadcasting, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9316
  • Type

    jour

  • DOI
    10.1109/11.486076
  • Filename
    486076